Dynamic random access memory with fet equalization of bit lines

ABSTRACT

A dynamic random access memory with a folded bit line structure (BLL j1 , BLL j1 , BLR j1  BLR j1 ), each pair of bit lines being divided into a plurality of blocks (MCB j1 , MCB j2 ), comprises equalizing transistors (Q j9 , Q j10 ) each of which is provided for each pair of divided bit lines to equalize the pair of divided bit lines. The equalizing transistors (Q j9 , Q j10 ) stop equalizing selectively and at different times among the blocks.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a dynamic random access memory(hereinafter referred to as DRAM), and more particularly, it relates toa CMOS-DRAM employing a (1/2) V_(CC) precharge system, i.e., a system ofprecharging bit lines at (1/2) V_(CC) by equalizing means.

2. Description of the Prior Art

A dynamic RAM generally comprises memory cell array blocks. Each of theblocks has a plurality of memory cells, and each of the memory cells isformed by a transistor and a capacitor. As the ratio of the capacitanceof a bit line to that of the capacitor of the memory cell is decreased,potential variation of the bit line in data reading is increased so thatinput potential difference for a sense amplifier is increased, whereby aread operation is reliably performed.

However, the memory cell size is reduced as a memory having a largercapacity is implemented with higher density of integration, whereby thememory cell capacitance is decreased while the number of memory cellsconnected to a bit line is increased. Therefore, the bit line isenlarged in length and the capacitance thereof is increased. Thus, theratio of the bit line capacitance to the memory cell capacitance may beso increased that a read operation cannot be reliably performed. Inorder to solve such a problem, there is an attempt to divide a bit lineinto a plurality of blocks to reduce the ratio of the bit linecapacitance to the memory cell capacitance.

FIG. 1 shows the entire structure of a conventional basic DRAM.

Referring to FIG. 1, the conventional DRAM comprises a memory part 1including a memory cell array formed by a plurality of memory cellsarrayed in the form of a matrix, a row decoder for selecting a row fromthe memory cell array and a column decoder for selecting a column fromthe memory cell array. Provided as peripheral circuits are a clockgeneration circuit 2 for generating various operation timing signals inresponse to an externally supplied clock signal RAS, an address buffer 3for strobing externally supplied address signals A₀ to A_(n) in responseto a control signal (internal RAS) from the clock generation circuit 2to generate an internal address signal and supply the same to the rowdecoder and the column decoder of the memory part 1, a data input buffer4 for receiving input data D_(IN) in response to a control signal fromthe clock generation circuit 2 and transmitting the same to the memorypart 1 and a data output buffer 5 for receiving data read from thememory part 1 in response to a control signal from the clock generationcircuit 2 and transferring output data D_(OUT) to the exterior.

The clock signal RAS is supplied to a terminal 10. The external addresssignals A₀ to A_(n) are supplied to terminals 11-0 to 11-n,respectively. The input data D_(IN) is supplied to a terminal 12. Theoutput data D_(OUT) is transmitted from a terminal 13 to the exterior ofthe DRAM. A power terminal 14 for receiving supply voltage V_(CC) and aground terminal 15 connected to a ground potential V_(SS) are furtherprovided in order to supply operating voltage to the DRAM. The memorypart 1 and the peripheral circuits are integrated on a semiconductorchip 16.

FIG. 2 shows exemplary structure of the memory part 1 of the DRAM asshown in FIG. 1.

Referring to FIG. 2, the memory cell array is divided into eight memorycell array blocks ML₁, ML₂, ML₃ and ML₄ and MR₁, MR₂, MR₃ and MR₄. Acolumn decoder is provided for four memory cell array blocks. Namely, acolumn decoder CL is provided for the left memory cell array blocks ML₁to ML₄ and another column decoder CR is provided for the right memorycell array blocks MR₁ to MR₄.

A shared sense amplifier block NSL₁ is provided between the memory cellarray blocks ML₁ and ML₂. Respective bit lines of the memory cell arrayblocks ML₁ and ML₂ are connected with each other through the sharedsense amplifier block NSL₁, to form one bit line. A sense amplifierblock PSL₁ is provided to detect and amplify information on each bitline of the memory cell array block ML₁, and a sense amplifier +I/Oblock PIL₁ is provided between the column decoder CL and the memory cellarray block ML₂ in order to detect and amplify information on each bitline of the memory cell array block ML₂.

The information on each bit line of the memory cell array block ML₁ isdetected and amplified by respective amplifiers of the sense amplifierblock PSL₁ and the shared sense amplifier block NSL₁. The information oneach bit line of the memory cell array block ML₂ is detected andamplified by respective amplifiers of the shared sense amplifier blockNSL₁ and the sense amplifier +I/O block PIL₁. One of the bit lines ofthe memory cell array blocks ML₁ and ML₂ is connected to a datainput/output bus through an I/O gate in the sense amplifier +I/O blockPIL₁ by output of the column decoder CL.

The remaining memory cell array blocks ML₃ and ML₄ are arranged in asimilar manner to the above. Namely, a sense amplifier +I/O block PIL₂is provided between the column decoder CL and the memory cell arrayblock ML₃ and a shared sense amplifier block NSL₂ is provided betweenthe memory cell array blocks ML₃ and ML₄ while a sense amplifier blockPSL₂ is provided on the right end of the memory cell array block ML₄.

The right memory cell array blocks MR₁ to MR₄ are arranged symmetricallyto the left memory cell array blocks ML₁ to ML₄. A sense amplifier blockPSR₁ is provided for the memory cell array block MR₁, and a shared senseamplifier block NSR₁ is provided between the memory cell array blocksMR₁ and MR₂. A sense amplifier +I/O block PIR₂ is provided between thememory cell array block MR₂ and the column decoder CR. A sense amplifier+I/O block PIR₂ is provided between the column decoder CR and the memorycell array block MR₃. A shared sense amplifier block NSR₂ is providedbetween the memory cell array blocks MR₃ and MR₄, and a sense amplifierblock PSR₂ is provided on the right end of the memory cell array blockMR₄. Operation of each right block is functionally similar to that ofthe corresponding one of the left blocks.

A row decoder RD is provided for selecting a word line (a row) from thememory cell array blocks ML₁ to ML₄ and MR₁ to MR₄.

Description is now made on the structure of a bit line part selected byone of column decoder output, i.e., the structure of an adjacent pair ofmemory cell array blocks and a sense amplifier provided for the same.

FIG. 3 illustrates the structure of a bit line pair and a CMOS senseamplifier part of a conventional DRAM as described in, e.g., ISSCCDigest of Technical Papers 1984, pp. 278 to 279. This DRAM employs theso-called shared sense amplifier structure in which each bit line isdivided into a pair of divided bit lines to commonly share a senseamplifier with a divided bit line pair provided on both sides of thesame. Although transistors of memory cells are formed by P-channel FETsand the shared sense amplifier is formed by P-channel FETs and senseamplifiers on both ends are formed by N-channel FETs in the structuredescribed in the aforementioned literature, such FETs are reversed inconductivity type and the operation is slightly simplified in FIG. 3,for convenience of illustration.

Referring to FIG. 3, symbols MCB_(j1) and MCB_(j2) indicate memory cellarray blocks, each of which includes a plurality of word lines, aplurality of divided bit line pairs, memory cells, potential differenceamplifying means and equalizing means. Bit lines forming folded bitlines are divided into bit line pairs BLL_(j), BLL_(j) and BLR_(j),BLR_(j) respectively. Cross-coupled FETs Q_(j1) and Q_(j2) form anN-channel sense amplifier (potential difference amplifying means)NSA_(j), which is shared with the memory cell array blocks MCB_(j1) andMCB_(j2). Similarly cross-coupled FETs Q_(j5), Q_(j6) and Q_(j7), Q_(j8)are adapted to form P-channel sense amplifiers (potential differenceamplifying means) PSA_(jL) and PSA_(jR), respectively. The sources ofthe FETs Q_(j1) and Q_(j2) are commonly connected to the drain of an FETQ_(N), whose gate and source are connected to an N-channel senseamplifier driving signal S_(N) and a ground potential V_(SS),respectively. The sources of the FETs Q_(j5), Q_(j6) and Q_(j7), Q_(j8)are commonly connected to the drains of FETs Q_(PL) and Q_(PR)respectively, while the gate and the source of the FET Q_(PL) areconnected to a P-channel sense amplifier driving signal S_(PL) and asupply potential V_(CC) respectively, and the gate and the source of theFET Q_(PR) are connected to a P-channel sense amplifier driving signalS_(PR) and a supply potential V_(CC), respectively.

The P-channel sense amplifier PSA_(jL) is connected to the divided bitlines BLL_(j) and BLL_(j) and the P-channel sense amplifier PSA_(jR) isconnected to the divided bit lines BLR_(j) and BLR_(j). Transfer gateFETs Q_(j11) and Q_(j12) are provided between the divided bit linesBLL_(j) and BLL_(j) and the N-channel sense amplifier NSA_(j) whiletransfer gate FETs Q_(j13) and Q_(j14) are provided between the dividedbit lines BLR_(j) and BLR_(j) and the N-channel sense amplifier NSA_(j).The gates of the FETs Q_(j11), Q_(j12) and Q_(j13), Q_(j14) receive thetransfer signals SL and SR, respectively. FETs Q_(j9) and Q_(j10) areprovided for equalizing the divided bit line pairs BLL_(j), BLL_(j) andBLR_(j), BLR_(j), respectively, and the gates thereof receive equalizingsignals EQ.

The divided bit lines BLR_(j) and BLR_(j) are connected to bus lines BUand BU, respectively, through column gate FETs Q_(j15) and Q_(j16),whose gates are connected to a column selecting signal Y_(j). Although aplurality of memory cells are generally connected to such divided bitlines in accordance with memory capacity, for simplicity is representeda memory cell MC_(ij) connected to the divided bit line BLL_(j) in FIG.3. The memory cell MC_(ij) is formed by a capacitor C_(ij) and an FETQ_(ij), and the gate of the FET Q_(ij) is connected to a word lineWL_(i). An electrode of the capacitor C_(ij) is connected to a memorycell plate potential V_(SG).

Description is now made on an operation of the CMOS sense amplifierstructure as shown in FIG. 3 in the case of reading data "1" stored inthe capacitor C_(ij) of the memory cell MC_(ij), with reference to FIG.4 showing an operating waveform diagram.

The DRAM enters an activated state on the falling edge of an externalRAS signal (hereinafter referred to as Ext. RAS signal) as shown in FIG.4. In this activated state, an external row address signal is latched inthe interior of the chip on the falling edge of the Ext. RAS signal.Then the equalizing signal EQ and the transfer signal SR are turned tolow levels to stop equalization of the divided bit lines BLL_(j),BLL_(j) and BLR_(j), BLR_(j) while separating the divided bit linesBLR_(j) and BLR_(j) from the N-channel sense amplifier NSA. At thistime, the transfer signal SL is maintained at a high level.

Then, a potential of a word line selected in response to the row addresssignal latched in the chip interior goes high. It is assumed here thatthe word line WL_(i) of FIG. 3 is selected. When the potential of theword line WL_(i) thus goes high, the FET Q_(ij) enters an ON state sothat the charge stored in the capacitor C_(ij) is transferred to thedivided bit line BLL_(j), whereby the potential of the divided bit lineBLL_(j) exceeds the level as is equalized, i.e., (V_(CC) -V_(SS))/2.Then, the sense amplifier driving signals S_(N) and S_(PL) are turned tohigh and low levels, respectively, whereby the FETs Q_(N) and Q_(PL) areturned on so that the N-channel sense amplifier NSA_(j) and theP-channel sense amplifier PSA_(jL) operate to amplify the potentialdifference between the divided bit lines BLL_(j) and BLL_(j).

Then, the transfer signal SR again goes high so that the potentials ofthe divided bit lines BLL_(j) and BLL_(j) are transferred to the dividedbit lines BLR_(j) and BLR_(j). As the result, the potentials of thedivided bit lines BLR_(j) and BLR_(j) go high and low, respectively.Then, the sense amplifier driving signal S_(PR) goes low and the FETQ_(PR) enters an ON state so that the P-channel sense amplifier PSA_(jR)operates, whereby the potential of the divided bit line BLR_(j) israised to a higher level. Then, the column selecting signal Y_(j) goeshigh so that the potentials of the divided bit lines BLR_(j) and BLR_(j)are transferred to the bus lines BU and BU, whereby the data "1" storedin the capacitor C_(ij) of the memory cell MC_(ij) is read out.

When the Ext. RAS signal goes high so that the DRAM enters aninactivated state, the potential of the selected word line WL_(i) goeslow and the FET Q_(ij) in the memory MC_(cj) enters an OFF state. Thenthe sense amplifier driving signal S_(N) is turned to a low level andthe signals S_(PL) and S_(PR) are turned to high levels. Further, theequalizing signals EQ and the transfer signals SL and SR are turned tohigh levels, whereby the divided bit lines BLL_(j), BLL_(j) and BLR_(j)and BLR_(j) are equalized so that the respective potentials thereof areaveraged to the level of (V_(CC) -V_(SS))/2, while the paired dividedbit lines are connected with each other at the same time.

The aforementioned various control signals are produced by circuits asshown in FIG. 5. Description is now made on the structure of eachcontrol signal producing circuit.

The equalizing signal EQ is produced by a delay circuit 51 for delayingthe clock signal RAS by a predetermined time t₂ and an equalizing signalgenerator 52 formed by a buffer for waveform-shaping output from thedelay circuit 51 and outputting the same.

A word line driving signal WL_(i) is produced by a row decoder 53. Therow decoder 53 decodes an internal row address from an address buffer 54for receiving an external address and producing an internal address toselect a word line WL_(i), thereby to make the potential of the selectedword line rise in response to a signal from a delay circuit 55 fordelaying the clock signal RAS by a time t₃.

The NMOS sense amplifier driving signal S_(N) is produced by a delaycircuit 56 for delaying the word line driving signal WL_(i) by a time t₄and outputting the same and an NMOS sense amplifier driving signalgenerator 57 formed by a buffer for waveform-shaping output from thedelay circuit 56 and outputting the same.

The transfer signal SL is produced by a left transfer signal generator60 activated in response to a block selecting address from the addressbuffer 54 for generating a signal which falls in response to a signalfrom a delay circuit 58 for delaying the clock signal RAS by a time t₁while rising in response to output from a delay circuit 59 for delayingthe NMOS sense amplifier driving signal S_(N) by a time t₆.

The transfer signal SR is produced by a right transfer signal generator61 activated in response to a block selecting address from the addressbuffer 54 for generating a signal which falls in response to the outputfrom the delay circuit 58 while rising in response to the output fromthe delay circuit 59.

The PMOS sense amplifier driving signal S_(PL) is produced by a leftPMOS sense amplifier driving circuit 64 activated in response to a blockselecting address from the address buffer 54 for generating a signalwhich goes low in response to either output from a delay circuit 62 fordelaying the sense amplifier driving signal S_(N) by a time t₅ or outputfrom a delay circuit 63 for delaying the sense amplifier driving signalS_(N) by a time t₇.

The PMOS sense amplifier driving signal S_(PR) is produced by a rightPMOS sense amplifier activating circuit 65 activated by a blockselecting address from the address buffer 54 for generating a signalwhich falls in response to either output from the delay circuit 62 or63.

The falling timing of the sense amplifier driving signals S_(PL) andS_(PR) is determined by the block selecting address.

The column selecting signal Y_(j) is produced by a column decoder 67.The column decoder 67 decodes a column address from the address buffer54 to generate a signal Y_(j) which rises in response to output of adelay circuit 66 for delaying the NMOS sense amplifier driving signalS_(N) by a time t₈ to select a pair of bit lines and connect the same tothe data input/output buses BU and BU.

When the word line WL_(i) in the left-side block is selected in theconventional dynamic random access memory as hereinabove described, thedata stored in the memory cell is first read on the divided bit linesBLL_(j) and BLL_(j), to be then transferred to the divided bit linesBLR_(j) and BLr_(j). On the other hand, since the left and right dividedbit line pairs BLL_(j), BLL_(j) and BLR_(j) are equalized by the samesignals EQ, equalization of these divided bit line pairs issimultaneously stopped. Consequently, when a word line in the leftmemory block is selected, the right-side divided bit lines BLR_(j) andBLR_(j) enter electrically floating states after the equalizing signalEQ goes low, to be maintained in such states until the transfer signalSR again goes high. Such an interval is about 5 to 15 nsec. in general.In this interval, the left-side divided bit lines BLL_(j) and BLL_(j)perform a sensing operation. During the sensing operation, one of thedivided bit lines BLL_(j) and BLL_(j), i.e., BLL_(j) in this case, isdischarged to the ground potential V_(SS) while the other one, i.e.,BLL_(j) in this case, is charged to the power supply potential V_(CC).Such sensing operation is simultaneously performed in a number ofdivided bit line pairs coupled to memory cells which are connected tothe selected word line WL_(i), whereby the levels of the groundpotential V_(SS) and the supply potential V_(CC) are varied to causenoise. The right-side divided bit lines BLR_(j) and BLR_(j) are infloating states at the time when such noise is caused, to be subjectedto potential deviation by such noise.

When the divided bit lines BLR_(j) and BLR_(j) are affected by noise ina direction opposite to the potentials to be originally effected, ittakes time to discharge and charge the divided bit lines BLR_(j) andBLR_(j), respectively, whereby the sensing time is increased by Δt ascompared with the case in which no such noise is produced, to delay theaccess time.

A method of equalizing a bit line pair is described in U.S. Pat. No.4,397,003 to Wilson et al., for example. However, this prior art takesno account of a divided bit line pair or noise applied to the dividedbit line pair.

As a relevant prior art, there exist U.S. patent application Ser. Nos.014837, 020192 and 027536 by the same applicant. These prior artdisclose a DRAM having a divided line pair structure and the sameequalizing timing.

SUMMARY OF THE INVENTION

The present invention has been proposed to overcome the aforementioneddisadvantage, and an object thereof is to provide a high-speed dynamicRAM having large operating margins, which can prevent potentials of apair of divided bit lines from being unbalanced before starting ofsensing operation for the paired divided bit lines.

In the dynamic random access memory according to the present invention,bit lines are divided into a plurality of divided bit line pair byswitching means while equalizing FETs are provided for the respectivedivided bit line pairs, so that timings for stopping equalization by theequalizing FETs are made to be different for each of memory cell arrayblocks including the divided bit line pairs.

The timings for stopping equalization of the divided bit line pairs aremade to be different for each of the memory cell array blocks includingthe divided bit line pairs in the dynamic random access memory accordingto the present invention, whereby the floating time of each divided bitline pair before starting of sensing operation is reduced to preventincrease in sensing time due to potential difference caused in thedivided bit line pair by noise originating in sensing operation of otherdivided bit line pair.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates the entire structure of a conventionalDRAM;

FIG. 2 schematically illustrates the structure of a memory part of theconventional DRAM;

FIG. 3 specifically illustrates the structure of a bit line part of amemory cell array of the conventional DRAM;

FIG. 4 is a waveform diagram showing sensing operation of theconventional DRAM;

FIG. 5 illustrates the structure of respective control signal producingcircuits of the conventional DRAM;

FIG. 6 illustrates the structure of a bit line part of a memory cellarray of a DRAM according to an embodiment of the present invention;

FIG. 7 is a waveform diagram showing sensing operation of the DRAM asshown in FIG. 6;

FIG. 8 is a block diagram showing circuits for producing signals forcontrolling the operation of the DRAM as shown in FIG. 6;

FIG. 9 illustrates the structure of a bit line part of a memory cellarray of a DRAM according to another embodiment of the presentinvention;

FIG. 10 is a waveform diagram showing sensing operation of the DRAM asshown in FIG. 9;

FIG. 11 is a block diagram showing circuits for producing controlsignals for controlling the operation of the DRAM as shown in FIG. 9;and

FIG. 12 illustrates the structure of a bit line part of a memory cellarray of a DRAM according to still another embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Description is now made of embodiments of the present invention withreference to the accompanying drawings.

FIG. 6 illustrates the structure of a CMOS sense amplifier part and apaired bit line of a dynamic random access memory according to anembodiment of the present invention. Referring to FIG. 6, a bit linepair forming a folded bit line is divided into bit line pairs BLL_(j),BLL_(j) and BLR_(j), BLR_(j) by transfer gate FETs (switching means)Q_(j11), Q_(j12) and Q_(j13), Q_(j14). Namely, the bit line pair isdivided into two bit line pairs. An N-channel sense amplifier NSA_(j) isformed by cross-coupled FETs Q_(j1) and Q_(j2) and P-channel senseamplifiers PSA_(jL) and PSA_(jR) are formed by cross-coupled FETsQ_(j5), Q_(j6) and Q_(j7), Q_(j8), respectively. The sources of the FETsQ_(j1) and Q_(j2) are commonly connected to the drain of an FET Q_(N)which in turn has a gate and a source connected to an N-channel senseamplifier driving signal S_(N) and a ground potential V_(SS),respectively. The sources of the FETs Q_(j5), Q_(j6) and Q_(j7), Q_(j8)are commonly connected to the drains of FETs Q_(PL) and Q_(PR),respectively, while the gate and the source of the FET Q_(PL) areconnected to receive a P-channel sense amplifier driving signal S_(PL)and a supply potential V_(CC), respectively, and the gate and the sourceof the FET Q_(PR) are connected to receive a P-channel sense amplifierdriving signal S_(PR) and a supply potential V_(CC).

The P-channel sense amplifier PSA_(jL) is provided for the divided bitline pair BLL_(j) and BLL_(j) while the P-channel sense amplifierPSA_(jR) is provided for the divided bit line pair BLR_(j) and BLR_(j).Transfer gate FETs Q_(j11) and Q_(j12) are provided between the dividedbit lines BLL_(j) and BLL_(j) and the N-channel sense amplifier NSA_(j),while transfer gate FETs Q_(j13) and Q_(j14) are provided between thedivided bit lines BLR_(j) and BLR_(j) and the N-channel sense amplifierNSA_(j). Transfer signals SL and SR are supplied to the gates of theFETs Q_(j11), Q_(j12) and Q_(j13), Q_(j14), respectively. FETs Q_(j9)and Q_(j10) are adapted to equalize the divided bit line pairs BLL_(j),BLL_(j) and BLR_(j), BLR_(j), respectively, and the gates thereof areconnected with equalizing signals EQL and EQR, respectively. The dividedbit lines BLR_(j) and BLR_(j) are connected to bus lines BU and BUthrough column gate FETs Q_(j15) and Q_(j16), whose gates are connectedwith a column selecting signal Y_(j). Although a plurality of memorycells are connected to the divided bit lines in accordance with memorycapacity, for simplicity is represented a memory cell MC_(ij) connectedto the divided bit line BLL_(j) in FIG. 6. The memory cell MC_(ij) isformed by a capacitor C_(ij) and an FET Q_(ij), while the gate of theFET Q_(ij) is connected to a word line WL_(i). An electrode of thecapacitor C_(ij) is connected to a memory cell plate potential V_(SG).

Description is now made of operation of the CMOS sense amplifier part asshown in FIG. 6 in the case of reading data "1" stored in the capacitorC_(ij) of the memory cell MC_(ij), with reference to FIG. 7 showing anoperating waveform diagram.

The DRAM enters an activated state on the falling edge of an Ext. RASsignal as shown in FIG. 7. In this activated state, an external rowaddress signal is latched in the chip interior on the falling edge ofthe Ext. RAS signal. Then the equalizing signal EQL and the transfersignal SR are turned to low levels to stop equalization of the dividedbit lines BLL_(j) and BLL_(j) while separating the divided bit linesBLR_(j) and BLR_(j) from the N-channel sense amplifier NSA_(j). Thetransfer signal SL and the equalizing signal EQR are maintained at highlevels at this time.

Then, a potential of a word line selected in response to the row addresssignal latched in the chip interior is turned to a high level. It isassumed that the word line WL_(i) is selected in FIG. 6. When thepotential of the word line WL_(i) thus goes high, the FET Q_(ij) in thememory cell MC_(ij) enters an ON state so that the charge stored in thecapacitor C_(ij) is transferred to the divided bit line BLL_(j), wherebythe potential of the divided bit line BLL_(j) exceeds the level as isequalized, i.e., (V_(CC) -V_(SS))/2. Then the sense amplifier drivingsignals S_(N) and S_(PL) are turned to high and low levels,respectively, whereby the FETs Q_(N) and Q_(PL) enter ON states so thatthe N-channel sense amplifier NSA_(j) and the P-channel sense amplifierPSA_(jL) operate to amplify the potential difference between the paireddivided bit lines BLL_(j) and BLL_(j). Although noise is produced atthis time as hereinabove described with reference to the prior art, nopotential difference is introduced in the right-side divided bit linepair BLR_(j) and BLR_(j), since the same are continuously equalized asshown in FIG. 7.

Then the equalizing signal EQR goes low to stop equalization of thepaired divided bit lines BLR_(j) and BLR_(j). Further, the transfersignal SR again goes high so that the potentials of the divided bitlines BLL_(j) and BLL_(j) are transferred to the divided bit linesBLR_(j) and BLR_(j), respectively. As a result, the potentials of thedivided bit lines BLR_(j) and BLR_(j) go high and low, respectively.Then the sense amplifier driving signal S_(PR) goes low and the FETQ_(PR) enters an ON state so that the P-channel sense amplifier PSA_(jR)operates to raise the potential of the divided bit line BLR_(j) to ahigher level. Then the column selecting signal Y_(j) goes high and thepotentials of the divided bit lines BLR_(j) and BLR_(j) are transferredto the bus lines BU and BU, whereby the data "1" stored in the capacitorC_(ij) of the memory cell MC_(ij) is read out.

When the Ext. RAS signal goes high so that the DRAM enters aninactivated state, the potential of the selected word line WL_(i) goeslow and the FET Q_(ij) enters an OFF state. Then the sense amplifierdriving signal S_(N) is turned to a low level and the signals S_(PL) andS_(PR) are turned to high levels. Further, the equalizing signals EQLand EQR and the transfer signals SL and SR are turned to high levels,whereby the divided bit lines BLL_(j), BLL_(j) and BLR_(j), BLR_(j) areequalized and the respective potentials thereof are averaged to thelevel of (V_(CC) -V_(SS))/2, while the divided bit lines are connectedwith each other at the same time.

FIG. 8 shows the structure of circuits for producing the control signalsas shown in FIGS. 6 and 7. Referring to FIG. 8, description is now madeon the circuits for producing the control signals.

A word line driving signal WL_(i) is produced by a row decoder 53. Thisrow decoder 53 decodes a row address from an address buffer 54 to makethe potential of a selected word line rise in response to output from adelay circuit 71. The delay circuit 71 delays the clock signal RAS by atime t₃ and outputs the same. Thus, the word line driving signal WL_(i)rises after a lapse of the time t₃ from falling of the clock signal RAS.

The NMOS sense amplifier driving signal S_(N) is produced by a senseamplifier activating circuit 72. The sense amplifier activating circuit72 is formed by a buffer which receives output from a delay circuit 73for delaying the word line driving signal WL_(i) by a time t₄ towaveform-shape the same. Thus, the sense amplifier driving signal S_(N)rises after a lapse of the time t₄ from rising of the word line drivingsignal WL_(i).

The equlizing signal EQL is produced by a left bit line equalizingcircuit 74. The left bit line equalizing circuit 74 is activated by ablock selecting address (or row address) from an address buffer 54 togenerate a signal which enters an inactivated state ("L" level) inresponse to either output from a delay circuit 75 or 76. The delaycircuit 75 delays the clock signal RAS by a time t₂ to output the same.The delay circuit 76 delays the sense amplifier driving signal S_(N) bya time t₉ to output the same. The left bit line equalizing circuit 74generates a signal for stopping equalization (signal of "L" level) inresponse to the output of the delay circuit 75 when a row addressdesignates a word line in a left memory block while otherwise generatinga signal for stopping equalization in response to the output of thedelay circuit 76.

The equalizing signal EQR is produced by a right bit line equalizingcircuit 77. The right bit line equalizing circuit 77 is similar instructure to the left bit line equalizing circuit 74, and generates asignal which enters an inactivated state ("L" level) in response toeither output from the delay circuit 75 or 76 and to a row address(block selecting address).

The transfer signal SL is generated by a left transfer signal generationcircuit 78. The left transfer signal generation circuit 78 is activatedon the basis of a row address signal to generate a signal which falls inresponse to output from a delay circuit 79 while rising in response tooutput from a delay circuit 80. The delay circuit 79 delays the clocksignal RAS by a time t₁ to output the same. The delay circuit 80 delaysthe sense amplifier driving signal S_(N) by a time t₆ to output thesame. The left transfer signal generation circuit 78 is inactivated whena word line designated by the row address is included in a left memoryblock and is activated in other case.

The transfer signal SR is generated by a right transfer signalgeneration circuit 81. The right transfer signal generation circuit 81is similar in structure to the left transfer signal generation circuit78, and generates, in response to a row address signal (block selectingaddress), a signal which falls in response to the output from the delaycircuit 79 while rising in response to the output from the delay circuit80.

The left PMOS sense amplifier driving signal S_(PL) is generated by aleft PMOS sense amplifier activating circuit 82. The left PMOS senseamplifier activating circuit 82 generates, in response to a row address(or block selecting address), a signal which enters an activated state("L" level) in response to either output from a delay circuit 83 or 84.The delay circuit 83 delays the sense amplifier driving signal S_(N) bya time t₇ to output the same. The delay circuit 84 delays the senseamplifier driving signal S_(N) by a time t₅ to output the same. The leftPMOS sense amplifier activating circuit 82 generates a signal whichenters an activated state in response to the output from the delaycircuit 84 when the row address designates a word line in a left blockwhile generating a signal which enters an activated state in response tothe output from the delay circuit 83 in other case.

The right PMOS sense amplifier driving signal S_(PR) is generated by aright PMOS sense amplifier activating circuit 85. The right PMOS senseamplifier activating circuit 85 is similar in structure to the left PMOSsense amplifier activating circuit 85, and generates, on the basis of arow address (or block selecting address), a signal which enters anactivated state ("L" level) in response to either output from the delaycircuit 83 or 84.

The column selecting signal Y_(j) is generated by a column decoder 67.The column decoder 67 decodes a column address from the address buffer54 to select a column decoder output line connected to a pair of bitlines and make the selected output line go high in response to outputfrom a delay circuit 86. The delay circuit 86 delays the sense amplifierdriving signal S_(N) by a time t₈ to output the same.

With the aforementioned structure, the control signals respectivelyhaving predetermined delay times are generated from falling of the clocksignal RAS which in turn serves as a basic clock signal.

Although the aforementioned embodiment is in the so-called shared senseamplifier structure of sharing an N-channel sense amplifier with leftand right divided bit line pairs, N-channel sense amplifiers NSA_(jL)and NSA_(jR) and P-channel sense amplifiers PSA_(jL) and PSA_(jR) may beprovided for respective memory cell array blocks MCB_(j3) and MCB_(j4)as shown in FIG. 9. In this case, switching means may be formed only bytransfer gate FETs Q_(j17) and Q_(j18).

Description is briefly made of operation of the circuit as shown in FIG.9 for reading data "1" stored in a memory cell MC_(ij) with reference toFIG. 10 showing an operating waveform diagram thereof. When an Ext. RASsignal goes low, a transfer signal SR and an equalizing signal EQL forequalizing the left-side divided bit line pair are turned to low levels.Then, a word line WL_(i) selected by a row address signal is turned to ahigh level. Then sense amplifier driving signals S_(NL) and S_(PL)sequentially go high and low, whereby the sense amplifiers NSA_(jL) andPSA_(jL) sequentially operate to amplify the potential differencebetween divided bit lines BLL_(j) and BLL_(j). Then an equalizing signalEQR for equalizing the right-side divided bit line pair goes low to stopequalization. Then the transfer signal SR again goes high to transferthe potentials of the divided bit lines BLL_(j) and BLL_(j) to thedivided bit lines BLR_(j) and BLR_(j). Then the sense amplifier drivingsignals S_(NR) and S_(PR) sequentially go high and low, whereby thesense amplifiers NSA_(jR) and PSA_(jR) sequentially operate to amplifythe potential difference between the divided bit lines BLR_(j) andBLR_(j). Then a column selecting signal Y_(j) goes high so that thepotentials of the divided bit lines BLR_(j) and BLR_(j) are transferredto bus lines BU and BU, whereby the data is read out from the memorycell.

FIG. 11 illustrates the structure of circuits for producing the controlsignals as shown in FIGS. 9 and 10.

A word line driving signal WL_(i) is produced by a row decoder 100. Therow decoder 100 decodes an internal row address from an address buffer101 to select a single word line, thereby to make the potential of theselected word line rise in response to output from a delay circuit 102.The delay circuit 102 delays the clock signal RAS by a time t_(3a) tooutput the same.

The sense amplifier driving signal S_(NL) is produced by a left NMOSsense amplifier activating circuit 103. The left NMOS sense amplifieractivating circuit 103 generates, on the basis of a row address (orblock selecting address), a signal which rises in response to eitheroutput from a delay circuit 104 or 105. The delay circuit 104 delays theword line driving signal WL_(i) by a time t₄ to output the same. Thedelay circuit 105 delays a previously rising one of the driving signalsS_(NL) and S_(NR) by a time t₁₀ to output the same.

The sense amplifier driving signal S_(NR) is produced by a right NMOSsense amplifier activating circuit 106. The right sense amplifieractivating circuit 106 is similar in structure to the left senseamplifier activating circuit 103. On the basis of a row address (orblock selecting address), the right sense amplifier activating circuit106 generates a signal which rises in response to either output from thedelay circuit 104 or 105.

Each of the activating circuits 103 and 106 makes its signal rise inresponse to the output of the delay circuit 104 when the row address (orblock selecting address) designates a corresponding block, while makingits signal rise in response to the output from the delay circuit 105 inother case.

The transfer signal TR is produced by a transfer circuit 107. Thetransfer circuit 107 generates a signal which falls in response tooutput from a delay circuit 108 while rising in response to output froma delay circuit 109. The delay circuit 108 delays the clock signal RASby a time t₁ to output the same. The delay circuit 109 delays apreviously rising one of the output signals from the activating circuits103 and 106 by a time t_(6a) to output the same.

The equalizing signals EQL and EQR are produced by left and right bitline equalizing circuits 109 and 110, respectively. Each of the bit lineequalizing circuits 109 and 110 generates a signal which falls inresponse to either output from a delay circuit 111 or 112. Namely, eachof the bit line equalizing circuits 109 and 110 makes its signal fall inresponse to the output from the delay circuit 111 when the row addressdesignates a corresponding block while making its signal fall inresponse to the output from the delay circuit 112 in other case. Thedelay circuit 111 delays the clock signal RAS by a time t_(2a) to outputthe same. The delay circuit 112 delays a previously rising one of thedriving signals S_(NL) and S_(NR) by a time t₉ to output the same.

The PMOS sense amplifier driving signals S_(PL) and S_(PR) are producedby left and right sense amplifier activating circuits 113 and 114,respectively. Each of the sense amplifier activating circuits 113 and114 generates, on the basis of a row address (block selecting address),a signal which falls in response to either output from a delay circuit115 or 116. Namely, each of the sense amplifier activating circuits 113and 114 makes its signal fall in response to the output from the delaycircuit 115 when the row address designates a corresponding block, whilemaking its signal fall in response to the output from the delay circuit116 in other case. The delay circuit 115 delays a previously rising oneof the driving signals S_(NL) and S_(NR) by a time t₅ to output thesame. The delay circuit 116 delays a subsequently rising one of thedriving signals S_(NL) and S_(NR) by a time t₅ to output the same.

The column selecting signal Y_(j) is produced by a column decoder 117.The column decoder 117 decodes a column address from the address buffer101 to make an output signal line connected to a pair of bit lines risein response to output from a delay circuit 118 thereby to select a pairof bit lines. The delay circuit 118 delays a subsequently rising one ofthe sense amplifier driving signals S_(NL) and S_(NR) by a time t₁₁ tooutput the same.

Although the bit line pair is divided into two bit line pairs in each ofthe aforementioned embodiments, the same may be divided into a largernumber of bit line pairs while providing equalizing FETs for therespective divided bit line pairs so that timings for stoppingequalization are made different for each of the divided bit line pairs,as shown in FIG. 12.

According to the present invention as hereinabove described, the timingsfor stopping equalization of the divided bit line pairs are madedifferent for each of the memory cell array blocks, thereby to preventincrease in sensing time by potential difference introduced in eachdivided bit line pair due to noise resulting from a sensing operation inother memory cell block. Thus, a high-speed dynamic RAM having largeoperating margins can be obtained according to the present invention.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A dynamic random access memory comprising:memorycells arranged in a matrix of rows and columns, a plurality of wordlines each associated with a respective row and a plurality of bit linepairs each associated with a respective column, each bit line paircomprising a plurality of divided bit line pair sections, senseamplifying means for amplifying a potential difference of each saiddivided bit line pair section so that one divided bit line of arespective section is at a first potential and the other divided bitline of said respective section is at a second potential, and anequalizing means in each divided bit line pair section for couplingtogether bit lines of each divided bit line pair section in response toan equalizing signal, said equalizing means comprising first switchingmeans for receiving said equalizing signal; second switching means forcoupling said divided bit line pair sections of each bit line pair, andtiming controller means for applying activation signals to theequalizing means of each divided bit line pair section prior to asensing operation, said timing controller means comprising means forcontinuing equalization of a first divided bit line pair section of agiven bit line pair when a sensing operation begins in a second bit linepair section of said given bit line pair.
 2. A dynamic random accessmemory in accordance with claim 1, whereinsaid first and second senseamplifying means are sense amplifiers formed by N-channel FETs and senseamplifiers formed by P-channel FETs.
 3. A dynamic random access memoryin accordance with claim 1, whereinsaid equalizing means are N-channelFETs.
 4. A dynamic random access memory in accordance with claim 1,whereinsaid switching means are N-channel FETs.
 5. A dynamic randomaccess memory as recited in claim 1, wherein said timing controllermeans further comprises first means for terminating an activation signalapplied to said equalization means and second means for delayingtermination of an activation signal applied to the equalization means ofsaid first divided bit line pair section of said given bit line pairunitl after the sensing operation in said second bit line pair sectionof said given bit line pair has begun.
 6. A dynamic random access memoryas recited in claim 1, wherein only one of said divided bit line pairsincluded in one of said memory array blocks is connected to bus lineswithin said divided bit line pairs included in said plurality of memorycell array blocks.
 7. A dynamic random access memory as recited in claim1, wherein said equalizing means stop equalization immediately beforestarting of sensing operation in said memory cell array blocks includingsaid equalizing means.
 8. A dynamic random access memory as recited inclaim 1, wherein said timing controller means includes means forcontrolling said switching means to stop connection of adjacent ones ofsaid memory cell blocks in an interval between a predetermined timesubsequent to the start of a row address select signal and apredetermined time during the period of activation of the first andsecond sense amplifying means subsequent to the start thereof.
 9. Adynamic random access memory as recited in claim 1, wherein said memorycell block different from said memory cell array block including saidequalizing means adjacent to said memory cell array block including saidequalizing means.
 10. A dynamic random access memory comprising:aplurality of memory cell array blocks each including a plurality of wordlines a plurality of divided bit line pairs, and memory cells eachconnected to one of said divided bit line pairs and to one of said wordlines, first sense amplifying means for amplifying a potentialdifference of each said divided bit line pair so that one divided bitline is at a first potential, and second sense amplifying means foramplifying a potential difference of each said divided bit line pair sothat the other divided bit line is at a second potential, and equalizingmeans for equalizing respective ones of said divided bit line pairs,said equalizing means comprising FET means for coupling bit lines ofrespective divided bit line pairs, each said FET means having gateelectrode means for receiving equalizing signal; switching means forcoupling said divided bit line pairs of adjacent ones of said memorycell array blocks; timing controller means coupled to said equalizingmeans for controlling respective timings of said equalizing signalapplied to each said FET means of said equalizing means to stop saidequalizing means selectively and at different times among said memorycell blocks such that each said equalizing means is stopped aftersensing operation is started in a memory cell array block different fromthe memory cell array block including said equalizing means; whereinonly one of said divided bit line pairs included in one of said memoryarray blocks is connected to bus lines within said divided bit linepairs included in said plurality of memory cell array blocks.
 11. Adynamic random access memory comprising:a plurality of memory cell arrayblocks each including a plurality of word lines a plurality of dividedbit line pairs, and memory cells each connected to one of said dividedbit line pairs and to one of said word lines, first sense amplifyingmeans for amplifying a potential difference of each said divided bitline pair so that one divided bit line is at a first potential, andsecond sense amplifying means for amplifying a potential difference ofeach said divided bit line pair so that the other divided bit line is ata second potential, and equalizing means for equalizing respective onesof said divided bit lines pairs, said equalizing means comprising FETmeans for coupling bit lines of respective divided bit line pairs, eachsaid FET means having gate eletrode means for receiving an equalizingsignal; switching means for coupling said divided bit line pairs ofadjacent ones of said memory cell array blocks; timing controller meanscoupled to said equalizing means for controlling respective timings ofsaid equalizing signal applied to each said FET means of said equalizingmeans to stop said equalinzing means selectively and at different timesamong said memory cell blocks such that each equalizing means is stoppedafter sensing operation is started in a memory cell array blockdifferent from the memory cell array block including said equalizingmeans; wherein, said equalizing means stop equalization immediatelybefore starting of sensing operation in said memory cell array blocksincluding said equalizing means.
 12. A dynamic random access memorycomprising:a plurality of memory cell array blocks each including aplurality of word lines a plurality of divided bit line pairs, andmemory cells each connected to one of said divided bit line pairs and toone of said word lines, first sense amplifying means for amplifying apotential difference of each said divided bit line pair so that onedivided bit line is at a first potential, and second sense amplifyingmeans for amplifying a potential difference of each said divided bitline pair so that the other divided bit line is at a second potential,and equalizing means for equalizing respective ones of said divided bitline pairs, said equalizing means comprising FET means for coupling bitlines of respective divided bit line pairs, each said FET means havinggate electrode means for receiving an equalizing signal; switching meansfor coupling said divided bit line pairs of adjacent ones of said memorycell array blocks; timing controller means coupled to said equalizingmeans for controlling respective timings of said equalizing signalapplied to each said FET means of said equalizing means to stop saidequalizing means selectively and at different times among said memorycell blocks such that each said equalizing means is stopped aftersensing operation is started in a memory cell array block different fromthe memory cell array block including said equalizing means; said timingcontroller means includes means for controlling said switching means tostop connection of adjacent ones of said memory cell array blocks in aninterval between a predetermined time subsequent to the start of a rowaddress select signal and a predetermined time during the period ofactivation of the first and second sense amplifying means subsequent tothe start thereof.
 13. A dynamic random access memory comprising:aplurality of memory cell array blocks each including a plurality of wordlines a plurality of divided bit line pairs, and memory cells eachconnected to one of said divided bit line pairs and to one of said wordlines, first sense amplifying means for amplifying a potentialdifference of each said divided bit line pair so that one divided bitline is at a first potential, and second sense amplifying means foramplifying a potential difference of each said divided bit line pair sothat the other divided bit line is at a second potential, and equalizingmeans for equalizing respective ones of said divided bit line pairs,said equalizing means comprising FET means for coupling bit lines ofrespective divided bit line pairs, each said FET means having gateelectrode means for receiving an equalizing signal; switching means forcoupling said divided bit line pairs of adjacent ones of said memorycell array blocks; timing controller means coupled to said equalizingmeans for controlling respective timings of said equalizing signalapplied to each said FET means of said equalizing means to stop saidequalizing means selectively and at different times among said memorycell blocks such that each said equalizing means is stopped aftersensing operation is started in a memory cell array block different fromthe memory cell array block including said equalizing means; wherein,said memory cell block different from said memory cell array blockincluding said equalizing means is adjacent to said memory cell arrayblock including said equalizing means.
 14. A method of reducing noisegeneration within a dynamic random access memory comprising a pluralityof memory cell array blocks each including a plurality of word lines, aplurality of divided bit line pairs, and memory cells each connected toany of said divided bit line pairs and to any of said word lines, saiddynamic random access memory further comprising first sense amplifiermeans for amplifying a potential difference of each said divided bitline pair so that one divided bit line is at a first potential, secondsense amplifier means for amplifying a potential difference of each saiddivided bit line pair so that the other divided bit line is at a secondpotential and equalizing means for equalizing respective ones of saiddivided it line pairs, said equalizing means comprising FET means forcoupling each of said divided bit line pairs, said FET means having gateelectrode means for receiving an equalizing signal and switching meansfor coupling said divided bit line pairs between adjacent ones of saidmemory cell array blocks, said method comprising the steps ofcontrollingrespective timing of said equalizing signal applied to each said FETmeans and controlling said equalizing means to stop equalization by saidequalizing means selectively and at different times among said memorycell array blocks responsive to said equalizing signal such that eachsaid equalizing means is stopped after sensing operation is started in amemory cell array block different from the memory cell array blockincluding said equalizing means; wherein, said equalizing means stopequalization immediately before starting of sensing operation in saidmemory cell array block including said equalizing means.
 15. A method ofreducing noise generation within a dynamic random access memorycomprising memory cells arranged in a matrix of rows and columns, aplurality of word lines each associated with a respective row and aplurality of bit line pairs each associated with a respective column,each bit line pair comprising a plurality of divided bit line pairsections, sense amplifying means for amplifying a potential differenceof each said divided bit line pair section so that one divided bit lineof a respective section is at a first potential and the other dividedbit line of said respective section is at a second potential, anequalizing means in each divided bit line pair section for couplingtogether bit lines of each divided bit line pair section in response toan equalizing signal, said equalizing means comprising first switchingmeans for receiving said equalizing signal and second switching meansfor coupling said divided bit line pair sections of each bit line pair,said method comprising the steps ofapplying activation signals to theequalizing means of each divided bit line pair section for equalizationthereof prior to activation of a sense amplifier, terminatingequalization of a second divided bit line pair section of a selected bitline pair, activating a respective sense amplifier to sense and amplifythe potential difference of said second divided bit line pair section,and continuing equalization of a first divided bit line pair section ofsaid selected bit line pair at the time of activation of said senseamplifier.
 16. A method of reducing noise generation in a dynamic randomaccess memory as recited in claim 15, wherein said equalizing means stopequalization immediately before starting of sensing operation in saidmemory cell array block including said equalizing means.